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authorGaku Inami <gaku.inami.xw@bp.renesas.com>2014-06-03 14:03:10 +0200
committerSimon Horman <horms+renesas@verge.net.au>2014-06-17 12:58:21 +0200
commita57004eca542428a444025847098b2af4e52a81c (patch)
treec427ee0a5e1c99de4f82dc6976db272ab8644b0a /arch/arm/boot/dts/r8a7790-lager.dts
parentARM: shmobile: koelsch dts: Add VDD MPU regulator for DVFS (diff)
downloadlinux-a57004eca542428a444025847098b2af4e52a81c.tar.xz
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ARM: shmobile: r8a7791/koelsch dts: Add DVFS parameters into cpu0 node for r8a7791
Add needed information inside CPU0 for the generic cpufreq-cpu0 driver. - voltage-tolerance = 1% It reflects the tolerance for the CPU voltage defined inside the OPP table. Due to the lack of proper OPP definition, use an arbitrary safe value. - clock-latency = 300 us Approximate worst-case latency to do a full DVFS transition for every OPPs. Due to the lack of HW information, use an arbitrary safe value. Note: The term transition-latency will be more accurate to define this value since the clock transition latency is not the only parameter that will define the overall DVFS transition. - operating-points = < kHz - uV > List of 6 operating points. All of them are using the same voltage since DVS is not supported in R-CAR Gen2. - clocks phandle to the CPU clock source. This clock source is used for all the 2 CortexA15 located inside the same cluster. Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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