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authorGeert Uytterhoeven <geert+renesas@glider.be>2016-01-29 11:04:37 +0100
committerSimon Horman <horms+renesas@verge.net.au>2016-02-09 19:43:20 +0100
commit5fb544da5f9a77ef723b685181d4e763f6a1b2eb (patch)
treef64f572dd0880f7b269720e5c7877872ab2b1657 /arch/arm/boot/dts/r8a7790.dtsi
parentARM: dts: r8a7794: Rename the serial port clock to fck (diff)
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ARM: dts: r8a7778: Add BRG support for SCIF
Add the device node for the external SCIF_CLK. The presence of the SCIF_CLK crystal and its clock frequency depends on the actual board. Add the two optional clock sources (S1 and SCIF_CLK for the internal resp. external clock) for the Baud Rate Generator for External Clock (BRG) to all SCIF device nodes. This increases the range and accuracy of supported baud rates on SCIF. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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