diff options
| author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2016-07-14 22:19:44 +0200 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2016-08-08 12:53:00 +0200 |
| commit | 47db051c22a03d41eac0d8193f3fe37b4f9768e9 (patch) | |
| tree | 6072de49297a4fae9b9f7c75b9949efa411318d1 /arch/arm/boot/dts/r8a7792.dtsi | |
| parent | ARM: dts: r8a7792: add EtherAVB support (diff) | |
| download | linux-47db051c22a03d41eac0d8193f3fe37b4f9768e9.tar.xz linux-47db051c22a03d41eac0d8193f3fe37b4f9768e9.zip | |
ARM: dts: r8a7792: add CAN clocks
The R-Car CAN controllers can derive the CAN bus clock not only from
their peripheral clock input (clkp1) but also from the other internal
clock (clkp2) and the external clock fed on the CAN_CLK pin. Describe
those clocks in the R8A7792 device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7792.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7792.dtsi | 22 |
1 files changed, 20 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 37c9d95688cf..af8020bfc030 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -511,6 +511,13 @@ clock-div = <8>; clock-mult = <1>; }; + rcan_clk: rcan { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <49>; + clock-mult = <1>; + }; /* Gate clocks */ mstp1_clks: mstp1_clks@e6150134 { @@ -572,7 +579,8 @@ reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>; + <&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>, + <&cp_clk>, <&cp_clk>; #clock-cells = <1>; clock-indices = < R8A7792_CLK_GPIO7 R8A7792_CLK_GPIO6 @@ -580,12 +588,14 @@ R8A7792_CLK_GPIO3 R8A7792_CLK_GPIO2 R8A7792_CLK_GPIO1 R8A7792_CLK_GPIO0 R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10 + R8A7792_CLK_CAN1 R8A7792_CLK_CAN0 R8A7792_CLK_GPIO9 R8A7792_CLK_GPIO8 >; clock-output-names = "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", - "gpio11", "gpio10", "gpio9", "gpio8"; + "gpio11", "gpio10", "can1", "can0", + "gpio9", "gpio8"; }; }; @@ -604,4 +614,12 @@ /* This value must be overridden by the board. */ clock-frequency = <0>; }; + + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; }; |