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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2015-06-02 14:34:35 +0200 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2016-02-19 06:52:23 +0100 |
| commit | d12a384a1b264efd66a50cd5cb311c0d56aff681 (patch) | |
| tree | 8c3a2dd797cb7d0f249ddd243c57b57da796c198 /arch/arm/boot/dts/r8a7794.dtsi | |
| parent | ARM: dts: r8a7793: Add L2 cache-controller node (diff) | |
| download | linux-d12a384a1b264efd66a50cd5cb311c0d56aff681.tar.xz linux-d12a384a1b264efd66a50cd5cb311c0d56aff681.zip | |
ARM: dts: r8a7794: Add L2 cache-controller node
Add a device node for the L2 cache, and link the CPU nodes to it.
The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7794.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7794.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index df0861e84a4b..21a02df3609b 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -40,6 +40,7 @@ compatible = "arm,cortex-a7"; reg = <0>; clock-frequency = <1000000000>; + next-level-cache = <&L2_CA7>; }; cpu1: cpu@1 { @@ -47,9 +48,16 @@ compatible = "arm,cortex-a7"; reg = <1>; clock-frequency = <1000000000>; + next-level-cache = <&L2_CA7>; }; }; + L2_CA7: cache-controller@1 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; |