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| author | Phil Edworthy <phil.edworthy@renesas.com> | 2018-09-27 15:59:22 +0200 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2018-11-28 13:55:14 +0100 |
| commit | ddeec86cb608cc520bd69ab568135ee45d500595 (patch) | |
| tree | ae4440a61245477594e41e3a46d78be94b5f49b3 /arch/arm/boot/dts/r9a06g032.dtsi | |
| parent | Linux 4.20-rc1 (diff) | |
| download | linux-ddeec86cb608cc520bd69ab568135ee45d500595.tar.xz linux-ddeec86cb608cc520bd69ab568135ee45d500595.zip | |
ARM: dts: r9a06g032: Add pinctrl node
This provides a pinctrl driver for the Renesas R9A06G032 SoC
Based on a patch originally written by Michel Pollet at Renesas.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r9a06g032.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r9a06g032.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index eaf94976ed6d..2322268bc862 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -165,6 +165,14 @@ status = "disabled"; }; + pinctrl: pin-controller@40067000 { + compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl"; + reg = <0x40067000 0x1000>, <0x51000000 0x480>; + clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>; + clock-names = "bus"; + status = "okay"; + }; + gic: gic@44101000 { compatible = "arm,cortex-a7-gic", "arm,gic-400"; interrupt-controller; |