diff options
| author | Douglas Anderson <dianders@chromium.org> | 2019-04-12 01:21:55 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2019-04-12 13:14:29 +0200 |
| commit | 8a5deb4e316a5469f137e62eb1bbf6147ddbfd3d (patch) | |
| tree | 0f9d0ae62cf8db773c75924d0285c4ee8e4815ad /arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | |
| parent | ARM: dts: rockchip: Add dynamic-power-coefficient for rk3288 (diff) | |
| download | linux-8a5deb4e316a5469f137e62eb1bbf6147ddbfd3d.tar.xz linux-8a5deb4e316a5469f137e62eb1bbf6147ddbfd3d.zip | |
ARM: dts: rockchip: Add DDR retention/poweroff to rk3288-veyron hogs
Even though upstream Linux doesn't yet go into deep enough suspend to
get DDR into self refresh, there is no harm in setting these pins up.
They'll only actually do something if we go into a deeper suspend but
leaving them configed always is fine.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi index 72c4754032e9..b9cc90f0f25c 100644 --- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi @@ -229,6 +229,8 @@ &pinctrl { pinctrl-0 = < /* Common for sleep and wake, but no owners */ + &ddr0_retention + &ddrio_pwroff &global_pwroff /* Wake only */ @@ -236,6 +238,8 @@ >; pinctrl-1 = < /* Common for sleep and wake, but no owners */ + &ddr0_retention + &ddrio_pwroff &global_pwroff /* Sleep only */ |