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| author | Heiko Stuebner <heiko@sntech.de> | 2015-08-06 22:57:08 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2016-04-01 18:33:41 +0200 |
| commit | 1ab0c304a029fe3f2338c505b81df02d4220dbc7 (patch) | |
| tree | 68314071f589365e0bce23781c9da514b64e003f /arch/arm/boot/dts/rk3288-veyron.dtsi | |
| parent | ARM: dts: rockchip: remove broken-cd from emmc and sdio (diff) | |
| download | linux-1ab0c304a029fe3f2338c505b81df02d4220dbc7.tar.xz linux-1ab0c304a029fe3f2338c505b81df02d4220dbc7.zip | |
ARM: dts: rockchip: update rk3288-veyron cpu operating points
The generic operating points specified in rk3288.dtsi are specified by
Rockchip as conservative and for all cases.
In contrast the Veyron ChromeOS devices are supposed to use a special
chip variant often called rk3288-c and use different operating points
in their kernel also including a higher max frequency.
So override the operating points for veyron devices.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Diffstat (limited to 'arch/arm/boot/dts/rk3288-veyron.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/rk3288-veyron.dtsi | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index bfb20c878384..b2557bf5a58f 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -141,6 +141,22 @@ &cpu0 { cpu0-supply = <&vdd_cpu>; + operating-points = < + /* KHz uV */ + 1800000 1400000 + 1704000 1350000 + 1608000 1300000 + 1512000 1250000 + 1416000 1200000 + 1200000 1100000 + 1008000 1050000 + 816000 1000000 + 696000 950000 + 600000 900000 + 408000 900000 + 216000 900000 + 126000 900000 + >; }; &emmc { |