diff options
| author | Heiko Stuebner <heiko@sntech.de> | 2015-11-19 22:22:28 +0100 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2016-01-25 15:00:03 +0100 |
| commit | 219a5859c855b1e6e2663eb63a7f942a6bbdfb52 (patch) | |
| tree | 4b9b5175b028bcfb20a9d7b466dbf1252878d7bb /arch/arm/boot/dts/rk3288-veyron.dtsi | |
| parent | clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for i2s_2ch (diff) | |
| download | linux-219a5859c855b1e6e2663eb63a7f942a6bbdfb52.tar.xz linux-219a5859c855b1e6e2663eb63a7f942a6bbdfb52.zip | |
clk: rockchip: fix usbphy-related clocks
The otgphy clocks really only drive the phy blocks. These in turn
contain plls that then generate the 480m clocks the clock controller
uses to supply some other clocks like uart0, gpu or the video-codec.
So fix this structure to actually respect that hirarchy and removed
that usb480m fixed-rate clock working as a placeholder till now, as
this wouldn't even work if the supplying phy gets turned off while
its pll-output gets used elsewhere.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Michael Turquette <mturquette@baylibre.com>
Diffstat (limited to 'arch/arm/boot/dts/rk3288-veyron.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/rk3288-veyron.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 9fce91ffff6f..cb27a8f5a8e2 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -421,7 +421,7 @@ status = "okay"; assigned-clocks = <&cru SCLK_USBPHY480M_SRC>; - assigned-clock-parents = <&cru SCLK_OTGPHY0>; + assigned-clock-parents = <&usbphy0>; dr_mode = "host"; }; |