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| author | Simon Xue <xxm@rock-chips.com> | 2017-08-03 04:04:03 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2017-08-06 12:55:07 +0200 |
| commit | 1cc47e63599cb7be712c8966a50d79153f9b6877 (patch) | |
| tree | 4c07a212a622d1ba9cb664df4a530fa1cfa2854f /arch/arm/boot/dts/rk3288.dtsi | |
| parent | ARM: dts: rockchip: convert rk3288 device tree files to 64 bits (diff) | |
| download | linux-1cc47e63599cb7be712c8966a50d79153f9b6877.tar.xz linux-1cc47e63599cb7be712c8966a50d79153f9b6877.zip | |
ARM: dts: rockchip: add more iommu nodes on rk3288
Add IEP/ISP/VPU/HEVC iommu nodes
Signed-off-by: Simon Xue <xxm@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm/boot/dts/rk3288.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/rk3288.dtsi | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index b1995c0efb13..c0c04e99e159 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -953,6 +953,25 @@ status = "okay"; }; + iep_mmu: iommu@ff900800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff900800 0x0 0x40>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "iep_mmu"; + #iommu-cells = <0>; + status = "disabled"; + }; + + isp_mmu: iommu@ff914000 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "isp_mmu"; + #iommu-cells = <0>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + vopb: vop@ff930000 { compatible = "rockchip,rk3288-vop"; reg = <0x0 0xff930000 0x0 0x19c>; @@ -1126,6 +1145,24 @@ }; }; + vpu_mmu: iommu@ff9a0800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff9a0800 0x0 0x100>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "vpu_mmu"; + #iommu-cells = <0>; + status = "disabled"; + }; + + hevc_mmu: iommu@ff9c0440 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hevc_mmu"; + #iommu-cells = <0>; + status = "disabled"; + }; + gpu: mali@ffa30000 { compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard"; reg = <0x0 0xffa30000 0x0 0x10000>; |