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authorOtavio Salvador <otavio@ossystems.com.br>2018-11-26 18:35:05 +0100
committerHeiko Stuebner <heiko@sntech.de>2018-11-27 01:09:12 +0100
commit7d2cecb0849fbb4cb27bfa3828a5a52c57a50748 (patch)
tree0b95b9fae1526ed1786e96e27fe2a2fb549de858 /arch/arm/boot/dts/rv1108.dtsi
parentARM: dts: rockchip: Assign the proper GPIO clocks for rv1108 (diff)
downloadlinux-7d2cecb0849fbb4cb27bfa3828a5a52c57a50748.tar.xz
linux-7d2cecb0849fbb4cb27bfa3828a5a52c57a50748.zip
ARM: dts: rockchip: Add UART DMA support for rv1108
Pass the 'dmas' property to the UART ports so that DMA can be supported. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Tested-by: Fabio Berton <fabio.berton@ossystems.com.br> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm/boot/dts/rv1108.dtsi')
-rw-r--r--arch/arm/boot/dts/rv1108.dtsi6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 300de8e1475b..17dbcf2571fd 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -119,6 +119,8 @@
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
+ dmas = <&pdma 6>, <&pdma 7>;
+ #dma-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&uart2m0_xfer>;
status = "disabled";
@@ -133,6 +135,8 @@
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
+ dmas = <&pdma 4>, <&pdma 5>;
+ #dma-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer>;
status = "disabled";
@@ -147,6 +151,8 @@
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
+ dmas = <&pdma 2>, <&pdma 3>;
+ #dma-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
status = "disabled";