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authorClaudiu Beznea <claudiu.beznea@microchip.com>2021-10-20 11:46:55 +0200
committerNicolas Ferre <nicolas.ferre@microchip.com>2021-10-21 13:45:16 +0200
commit9430ff34385e285984711fccb2226771cbc675fb (patch)
tree2780a9d0d0a3227212157991312b2cbd2ca9f398 /arch/arm/boot/dts/sama7g5.dtsi
parentARM: dts: at91: sama7g5: add rtc node (diff)
downloadlinux-9430ff34385e285984711fccb2226771cbc675fb.tar.xz
linux-9430ff34385e285984711fccb2226771cbc675fb.zip
ARM: dts: at91: sama7g5: add tcb nodes
Add TCB nodes. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20211020094656.3343242-3-claudiu.beznea@microchip.com
Diffstat (limited to 'arch/arm/boot/dts/sama7g5.dtsi')
-rw-r--r--arch/arm/boot/dts/sama7g5.dtsi20
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
index 0912219ed5a1..c75c7d7c2842 100644
--- a/arch/arm/boot/dts/sama7g5.dtsi
+++ b/arch/arm/boot/dts/sama7g5.dtsi
@@ -144,6 +144,16 @@
clocks = <&clk32k 0>;
};
+ tcb1: timer@e0800000 {
+ compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xe0800000 0x100>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 91>, <&pmc PMC_TYPE_PERIPHERAL 92>, <&pmc PMC_TYPE_PERIPHERAL 93>, <&clk32k 1>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
+ };
+
adc: adc@e1000000 {
compatible = "microchip,sama7g5-adc";
reg = <0xe1000000 0x200>;
@@ -461,6 +471,16 @@
status = "disabled";
};
+ tcb0: timer@e2814000 {
+ compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xe2814000 0x100>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 88>, <&pmc PMC_TYPE_PERIPHERAL 89>, <&pmc PMC_TYPE_PERIPHERAL 90>, <&clk32k 1>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
+ };
+
flx8: flexcom@e2818000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xe2818000 0x200>;