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| author | Dinh Nguyen <dinguyen@opensource.altera.com> | 2013-11-20 16:39:17 +0100 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@opensource.altera.com> | 2015-07-22 20:16:51 +0200 |
| commit | c5dab6e2c1f7bbf33ec855cebae92a1566ed6d04 (patch) | |
| tree | dbd69f64bd7bc2dee0495ca914424ec04b791d1c /arch/arm/boot/dts/socfpga.dtsi | |
| parent | ARM: dts: socfpga: Add support of Terasic DE0 Atlas board (diff) | |
| download | linux-c5dab6e2c1f7bbf33ec855cebae92a1566ed6d04.tar.xz linux-c5dab6e2c1f7bbf33ec855cebae92a1566ed6d04.zip | |
ARM: socfpga: dts: Correct the parent clock for l3_sp_clk and dbg_clk
The l3_sp_clk's parent should be the l3_mp_clk. This will account for
the extra divider that is present for the l3_mp_clk.
The dbg_clk's parent should be the dbg_at_clk. This will account for
the extra divider that is present for the dbg_at_clk.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'arch/arm/boot/dts/socfpga.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/socfpga.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 1e3c833dfbd2..7860935ae3a2 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -318,7 +318,7 @@ l3_sp_clk: l3_sp_clk { #clock-cells = <0>; compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>; + clocks = <&l3_mp_clk>; div-reg = <0x64 2 2>; }; @@ -349,7 +349,7 @@ dbg_clk: dbg_clk { #clock-cells = <0>; compatible = "altr,socfpga-gate-clk"; - clocks = <&dbg_base_clk>; + clocks = <&dbg_at_clk>; div-reg = <0x68 2 2>; clk-gate = <0x60 5>; }; |