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authorDinh Nguyen <dinguyen@kernel.org>2016-12-20 05:34:00 +0100
committerDinh Nguyen <dinguyen@kernel.org>2017-01-05 13:12:54 +0100
commit6ed6bf47623fbcceb9a1187159a80c20f2874fcc (patch)
tree51503d5afe7c377af595a136d9def8a129e3a2e7 /arch/arm/boot/dts/socfpga.dtsi
parentARM: dts: socfpga: Add NAND device tree for Arria10 (diff)
downloadlinux-6ed6bf47623fbcceb9a1187159a80c20f2874fcc.tar.xz
linux-6ed6bf47623fbcceb9a1187159a80c20f2874fcc.zip
ARM: dts: socfpga: fpga manager data is 32 bits
Adjust regs property for the FPGA manager data register to properly reflect that it is a single 32 bit register. Signed-off-by: Dalon Westergreen <dwesterg@altera.com> Signed-off-by: Alan Tull <atull@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/socfpga.dtsi')
-rw-r--r--arch/arm/boot/dts/socfpga.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index da689659131f..de291724e0be 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -516,7 +516,7 @@
fpgamgr0: fpgamgr@ff706000 {
compatible = "altr,socfpga-fpga-mgr";
reg = <0xff706000 0x1000
- 0xffb90000 0x1000>;
+ 0xffb90000 0x4>;
interrupts = <0 175 4>;
};