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authorDinh Nguyen <dinguyen@opensource.altera.com>2016-03-23 21:40:54 +0100
committerDinh Nguyen <dinguyen@kernel.org>2016-04-11 21:04:06 +0200
commit249ff32e1f8b6ffa92e1390e371702dd8633bcac (patch)
treee764c77406ee94ab8c446a4918b7738f1bc0e5cb /arch/arm/boot/dts/socfpga_arria10.dtsi
parentARM: dts: socfpga: Add Altera Arria10 OCRAM EDAC devicetree entry (diff)
downloadlinux-249ff32e1f8b6ffa92e1390e371702dd8633bcac.tar.xz
linux-249ff32e1f8b6ffa92e1390e371702dd8633bcac.zip
ARM: dts: socfpga: add reset control for USB
Add the resets property for the 2 USB controllers. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'arch/arm/boot/dts/socfpga_arria10.dtsi')
-rw-r--r--arch/arm/boot/dts/socfpga_arria10.dtsi4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 4eec2c7f2167..17e81dc9213e 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -713,6 +713,8 @@
interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&usb_clk>;
clock-names = "otg";
+ resets = <&rst USB0_RESET>;
+ reset-names = "dwc2";
phys = <&usbphy0>;
phy-names = "usb2-phy";
status = "disabled";
@@ -724,6 +726,8 @@
interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&usb_clk>;
clock-names = "otg";
+ resets = <&rst USB1_RESET>;
+ reset-names = "dwc2";
phys = <&usbphy0>;
phy-names = "usb2-phy";
status = "disabled";