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| author | Thor Thayer <thor.thayer@linux.intel.com> | 2018-09-25 17:21:10 +0200 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2018-09-27 16:33:00 +0200 |
| commit | ce3bf934f919a7d675c5b7fa4cc233ded9c6256e (patch) | |
| tree | bf6a365c399e061ca520303c11403444c5fdd27b /arch/arm/boot/dts/socfpga_arria10.dtsi | |
| parent | ARM: dts: socfpga: add timer resets for SoCFPGA platform (diff) | |
| download | linux-ce3bf934f919a7d675c5b7fa4cc233ded9c6256e.tar.xz linux-ce3bf934f919a7d675c5b7fa4cc233ded9c6256e.zip | |
ARM: dts: socfpga: Fix SDRAM node address for Arria10
The address in the SDRAM node was incorrect. Fix this to agree with the
correct address and to match the reg definition block.
Cc: stable@vger.kernel.org
Fixes: 54b4a8f57848b("arm: socfpga: dts: Add Arria10 SDRAM EDAC DTS support")
Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/socfpga_arria10.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/socfpga_arria10.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 4e0c26423d84..59ef13e37536 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -628,7 +628,7 @@ status = "disabled"; }; - sdr: sdr@ffc25000 { + sdr: sdr@ffcfb100 { compatible = "altr,sdr-ctl", "syscon"; reg = <0xffcfb100 0x80>; }; |