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author | Dinh Nguyen <dinguyen@altera.com> | 2014-02-18 03:31:02 +0100 |
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committer | Dinh Nguyen <dinguyen@altera.com> | 2014-03-10 05:11:35 +0100 |
commit | 9b931361ff0971d2639b1366f8b468c687fa942f (patch) | |
tree | 7d38293deaeddd014219ddbb749d23a88f575d24 /arch/arm/boot/dts/socfpga_arria5.dtsi | |
parent | dts: socfpga: Update clock entry to support multiple parents (diff) | |
download | linux-9b931361ff0971d2639b1366f8b468c687fa942f.tar.xz linux-9b931361ff0971d2639b1366f8b468c687fa942f.zip |
dts: socfpga: Add support for SD/MMC on the SOCFPGA platform
Introduce "altr,socfpga-dw-mshc" to enable Altera's SOCFPGA platform
specific implementation of the dw_mmc driver.
Also add the "syscon" binding to the "altr,sys-mgr" node. The clock
driver can use the syscon driver to toggle the register for the SD/MMC
clock phase shift settings.
Finally, fix an indentation error for the sysmgr node.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Tested-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Chris Ball <chris@printf.net>
Diffstat (limited to 'arch/arm/boot/dts/socfpga_arria5.dtsi')
-rw-r--r-- | arch/arm/boot/dts/socfpga_arria5.dtsi | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi index a85b4043f888..6c87b7070ca7 100644 --- a/arch/arm/boot/dts/socfpga_arria5.dtsi +++ b/arch/arm/boot/dts/socfpga_arria5.dtsi @@ -27,6 +27,17 @@ }; }; + dwmmc0@ff704000 { + num-slots = <1>; + supports-highspeed; + broken-cd; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; + serial0@ffc02000 { clock-frequency = <100000000>; }; |