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| author | Linus Walleij <linus.walleij@linaro.org> | 2013-11-13 15:59:40 +0100 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2013-11-26 21:01:55 +0100 |
| commit | a12f703c5a27e2061fd0ea77200e5e2f8cfee54b (patch) | |
| tree | 7fe922b21ee34e0c1a1ea6971adc91d1f92df695 /arch/arm/boot/dts/ste-href-family-pinctrl.dtsi | |
| parent | ARM: ux500: move GPIO217/218 config to device tree (diff) | |
| download | linux-a12f703c5a27e2061fd0ea77200e5e2f8cfee54b.tar.xz linux-a12f703c5a27e2061fd0ea77200e5e2f8cfee54b.zip | |
ARM: ux500: move MUSB pin config to device tree
This moves the MUSB pin control table out of the board file
and into the device tree. Tie the config to the on-chip MUSB
device rather than the ab8500-usb device which is off-chip.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/ste-href-family-pinctrl.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/ste-href-family-pinctrl.dtsi | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi index 7408d3a898a5..6868fec95d64 100644 --- a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi +++ b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi @@ -488,6 +488,61 @@ }; }; }; + + + musb { + musb_default_mode: musb_default { + default_mux { + ste,function = "usb"; + ste,pins = "usb_a_1"; + }; + default_cfg1 { + ste,pins = + "GPIO256_AF28", /* NXT */ + "GPIO258_AD29", /* XCLK */ + "GPIO259_AC29", /* DIR */ + "GPIO260_AD28", /* DAT7 */ + "GPIO261_AD26", /* DAT6 */ + "GPIO262_AE26", /* DAT5 */ + "GPIO263_AG29", /* DAT4 */ + "GPIO264_AE27", /* DAT3 */ + "GPIO265_AD27", /* DAT2 */ + "GPIO266_AC28", /* DAT1 */ + "GPIO267_AC27"; /* DAT0 */ + ste,config = <&in_nopull>; + }; + default_cfg2 { + ste,pins = "GPIO257_AE29"; /* STP */ + ste,config = <&out_hi>; + }; + }; + + musb_sleep_mode: musb_sleep { + sleep_cfg1 { + ste,pins = + "GPIO256_AF28", /* NXT */ + "GPIO258_AD29", /* XCLK */ + "GPIO259_AC29"; /* DIR */ + ste,config = <&slpm_wkup_pdis_en>; + }; + sleep_cfg2 { + ste,pins = "GPIO257_AE29"; /* STP */ + ste,config = <&slpm_out_hi_wkup_pdis>; + }; + sleep_cfg3 { + ste,pins = + "GPIO260_AD28", /* DAT7 */ + "GPIO261_AD26", /* DAT6 */ + "GPIO262_AE26", /* DAT5 */ + "GPIO263_AG29", /* DAT4 */ + "GPIO264_AE27", /* DAT3 */ + "GPIO265_AD27", /* DAT2 */ + "GPIO266_AC28", /* DAT1 */ + "GPIO267_AC27"; /* DAT0 */ + ste,config = <&slpm_in_wkup_pdis_en>; + }; + }; + }; }; }; }; |