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| author | Alexandre Torgue <alexandre.torgue@foss.st.com> | 2022-02-21 14:15:08 +0100 |
|---|---|---|
| committer | Alexandre Torgue <alexandre.torgue@foss.st.com> | 2022-02-25 10:53:15 +0100 |
| commit | cb4b2d26c78a1707499bf60768e463032a221e3a (patch) | |
| tree | 5642573efafdb856eacceff8e4888e3725cdadae /arch/arm/boot/dts/stm32mp151.dtsi | |
| parent | ARM: dts: stm32: Correct masks for GIC PPI interrupts on stm32mp13 (diff) | |
| download | linux-cb4b2d26c78a1707499bf60768e463032a221e3a.tar.xz linux-cb4b2d26c78a1707499bf60768e463032a221e3a.zip | |
ARM: dts: stm32: Correct masks for GIC PPI interrupts on stm32mp15
Using GIC_CPU_MASK_SIMPLE(x), x should reflect the number of CPUs.
STM32MP151 is a single A7.
STM32MP153/157 is a dual A7.
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/stm32mp151.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/stm32mp151.dtsi | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 2171e7a97e92..f9aa9af31efd 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -45,10 +45,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; interrupt-parent = <&intc>; }; |