diff options
| author | Adam Sampson <ats@offog.org> | 2015-10-18 00:08:29 +0200 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2015-10-19 20:05:24 +0200 |
| commit | f5bad43b53cbcd1a017c6df3d1bf2c6412a465bd (patch) | |
| tree | 6dd19eb5a2944622c0e49a587993e1a4df0247fd /arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts | |
| parent | ARM: dts: sun6i: Add support for Sinlinx A31s SDK board (diff) | |
| download | linux-f5bad43b53cbcd1a017c6df3d1bf2c6412a465bd.tar.xz linux-f5bad43b53cbcd1a017c6df3d1bf2c6412a465bd.zip | |
ARM: dts: sun7i: Enable USB DRC on pcDuino v3 Nano
The OTG arrangement on the LinkSprite pcDuino v3 Nano is the same as the
pcDuino 1/2/3: the OTG port's 5V line is connected directly to the 5V
bus (it's not switchable), and the OTG port's ID pin is connected to PH4
on the A20.
Tested successfully in both host and device modes.
Signed-off-by: Adam Sampson <ats@offog.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts')
| -rw-r--r-- | arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts index beac431aa594..1757a6ad74e9 100644 --- a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts @@ -142,6 +142,10 @@ status = "okay"; }; +&otg_sram { + status = "okay"; +}; + &pio { ahci_pwr_pin_pcduino3_nano: ahci_pwr_pin@0 { allwinner,pins = "PH2"; @@ -157,6 +161,13 @@ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PH4"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + usb1_vbus_pin_pcduino3_nano: usb1_vbus_pin@0 { allwinner,pins = "PD2"; allwinner,function = "gpio_out"; @@ -211,7 +222,15 @@ status = "okay"; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>; + usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb1_vbus>; status = "okay"; |