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| author | Maxime Ripard <maxime.ripard@bootlin.com> | 2019-08-22 10:21:15 +0200 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@bootlin.com> | 2019-08-23 09:47:26 +0200 |
| commit | d2b9c64443013197fbb71984e85f4c9551ffe26c (patch) | |
| tree | 18da9b79c29fcc716b4c51297369dd794101d431 /arch/arm/boot/dts/sun7i-a20.dtsi | |
| parent | arm64: dts: allwinner: a64: Add A64 OlinuXino board (with eMMC) (diff) | |
| download | linux-d2b9c64443013197fbb71984e85f4c9551ffe26c.tar.xz linux-d2b9c64443013197fbb71984e85f4c9551ffe26c.zip | |
ARM: dts: sun7i: Add CSI0 controller
The CSI controller embedded in the A20 can be supported by our new driver.
Let's add it to our DT.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'arch/arm/boot/dts/sun7i-a20.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/sun7i-a20.dtsi | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 651d7fe6b8ba..524c1d5a7d0d 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -376,6 +376,17 @@ num-cs = <1>; }; + csi0: csi@1c09000 { + compatible = "allwinner,sun7i-a20-csi0"; + reg = <0x01c09000 0x1000>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI0>, + <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>; + clock-names = "bus", "mod", "isp", "ram"; + resets = <&ccu RST_CSI0>; + status = "disabled"; + }; + emac: ethernet@1c0b000 { compatible = "allwinner,sun4i-a10-emac"; reg = <0x01c0b000 0x1000>; @@ -775,6 +786,20 @@ }; /omit-if-no-ref/ + csi0_8bits_pins: csi-8bits-pins { + pins = "PE0", "PE2", "PE3", "PE4", "PE5", + "PE6", "PE7", "PE8", "PE9", "PE10", + "PE11"; + function = "csi0"; + }; + + /omit-if-no-ref/ + csi0_clk_pin: csi-clk-pin { + pins = "PE1"; + function = "csi0"; + }; + + /omit-if-no-ref/ emac_pa_pins: emac-pa-pins { pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", |