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| author | Chen-Yu Tsai <wens@csie.org> | 2017-05-31 09:58:20 +0200 |
|---|---|---|
| committer | Chen-Yu Tsai <wens@csie.org> | 2017-06-03 04:03:39 +0200 |
| commit | c80aec5e0596858f8e8b26fb4844969ea5eb66e7 (patch) | |
| tree | 5699bced84408141cac8238c7b0bc4ff020bf7ea /arch/arm/boot/dts/sun8i-a83t.dtsi | |
| parent | ARM: dts: sun8i: h3: Add initial NanoPi M1 Plus support (diff) | |
| download | linux-c80aec5e0596858f8e8b26fb4844969ea5eb66e7.tar.xz linux-c80aec5e0596858f8e8b26fb4844969ea5eb66e7.zip | |
ARM: sun8i: a83t: Add device node for PRCM
The A83T's PRCM has the same set of clocks and resets as the A64.
However, a few dividers are different. And due to the lack of a low
speed 32.768 kHz oscillator, a few of the clock parents are different.
The PRCM also has controls for various power domains. These are not
supported yet, neither in software nor in the device tree binding.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun8i-a83t.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/sun8i-a83t.dtsi | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 1dc4cfe81534..49aeb56970ba 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -270,5 +270,15 @@ #interrupt-cells = <3>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; }; + + r_ccu: clock@1f01400 { + compatible = "allwinner,sun8i-a83t-r-ccu"; + reg = <0x01f01400 0x400>; + clocks = <&osc24M>, <&osc16Md512>, <&osc16M>, + <&ccu 6>; + clock-names = "hosc", "losc", "iosc", "pll-periph"; + #clock-cells = <1>; + #reset-cells = <1>; + }; }; }; |