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| author | Chen-Yu Tsai <wens@csie.org> | 2017-05-24 05:06:16 +0200 |
|---|---|---|
| committer | Chen-Yu Tsai <wens@csie.org> | 2017-08-08 06:03:58 +0200 |
| commit | b99b8832e4c90be199647bdd03a96d08b2000dce (patch) | |
| tree | a0921259d2a066db031ee425686c4256bc06ceaa /arch/arm/boot/dts/sun8i-a83t.dtsi | |
| parent | ARM: dts: sun8i: a83t: h8homlet: Enable micro-SD card and onboard eMMC (diff) | |
| download | linux-b99b8832e4c90be199647bdd03a96d08b2000dce.tar.xz linux-b99b8832e4c90be199647bdd03a96d08b2000dce.zip | |
ARM: sun8i: a83t: Add device node and pinmux setting for RSB controller
The A83T has an RSB controller for talking to the PMIC and audio codec.
Add a device node for it. Since there is only one usable pinmux setting,
for it, add that as well.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun8i-a83t.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/sun8i-a83t.dtsi | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index d9b4372dbdf3..61304761e8f6 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -47,6 +47,7 @@ #include <dt-bindings/clock/sun8i-a83t-ccu.h> #include <dt-bindings/clock/sun8i-r-ccu.h> #include <dt-bindings/reset/sun8i-a83t-ccu.h> +#include <dt-bindings/reset/sun8i-r-ccu.h> / { interrupt-parent = <&gic>; @@ -379,6 +380,28 @@ #gpio-cells = <3>; interrupt-controller; #interrupt-cells = <3>; + + r_rsb_pins: r-rsb-pins { + pins = "PL0", "PL1"; + function = "s_rsb"; + drive-strength = <20>; + bias-pull-up; + }; + }; + + r_rsb: rsb@1f03400 { + compatible = "allwinner,sun8i-a83t-rsb", + "allwinner,sun8i-a23-rsb"; + reg = <0x01f03400 0x400>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu CLK_APB0_RSB>; + clock-frequency = <3000000>; + resets = <&r_ccu RST_APB0_RSB>; + pinctrl-names = "default"; + pinctrl-0 = <&r_rsb_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; }; }; |