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| author | Maxime Ripard <maxime.ripard@free-electrons.com> | 2017-08-24 15:48:26 +0200 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2017-09-17 12:04:28 +0200 |
| commit | e488af71aa6704f327de6a7df7ae91df8f2997a0 (patch) | |
| tree | 7b5fd8271513841b81a6b3273815fbcf920acdfd /arch/arm/boot/dts/sun8i-a83t.dtsi | |
| parent | arm: dts: sun8i: a83t: Add MMC1 pins (diff) | |
| download | linux-e488af71aa6704f327de6a7df7ae91df8f2997a0.tar.xz linux-e488af71aa6704f327de6a7df7ae91df8f2997a0.zip | |
arm: dts: sun8i: a83t: Add the UART1 controller
The A83T has an UART1 controller, with the RTS and CTS pins routed so it
can be used for devices with hardware flow control, like a bluetooth chip.
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun8i-a83t.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/sun8i-a83t.dtsi | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 91dee798f3ca..a9032c238533 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -373,6 +373,16 @@ pins = "PF2", "PF4"; function = "uart0"; }; + + uart1_pins: uart1-pins { + pins = "PG6", "PG7"; + function = "uart1"; + }; + + uart1_rts_cts_pins: uart1-rts-cts-pins { + pins = "PG8", "PG9"; + function = "uart1"; + }; }; timer@1c20c00 { @@ -417,6 +427,17 @@ status = "disabled"; }; + uart1: serial@01c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + status = "disabled"; + }; + gic: interrupt-controller@1c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, |