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authorHans de Goede <hdegoede@redhat.com>2016-02-24 00:03:16 +0100
committerMaxime Ripard <maxime.ripard@free-electrons.com>2016-02-25 20:38:42 +0100
commitfe0a8ea1fb0b736c84ea763fcc30fffaed4efd14 (patch)
tree4256530843ddd65b7ff773b887dc9b49c3d26b87 /arch/arm/boot/dts/sun8i-h3.dtsi
parentARM: dts: sun8i-h3: Add R_PIO controller node to the dtsi (diff)
downloadlinux-fe0a8ea1fb0b736c84ea763fcc30fffaed4efd14.tar.xz
linux-fe0a8ea1fb0b736c84ea763fcc30fffaed4efd14.zip
ARM: dts: sun8i: Add ir receiver nodes to H3 dtsi
The H3 ir receiver is completely compatible with the one found in the A31. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun8i-h3.dtsi')
-rw-r--r--arch/arm/boot/dts/sun8i-h3.dtsi25
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index c3b73d7f074d..dadb7f60c062 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -295,6 +295,14 @@
clock-indices = <0>, <1>;
clock-output-names = "apb0_pio", "apb0_ir";
};
+
+ ir_clk: ir_clk@01f01454 {
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01f01454 0x4>;
+ #clock-cells = <0>;
+ clocks = <&osc32k>, <&osc24M>;
+ clock-output-names = "ir";
+ };
};
soc {
@@ -519,6 +527,16 @@
#reset-cells = <1>;
};
+ ir: ir@01f02000 {
+ compatible = "allwinner,sun5i-a13-ir";
+ clocks = <&apb0_gates 1>, <&ir_clk>;
+ clock-names = "apb", "ir";
+ resets = <&apb0_reset 1>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x01f02000 0x40>;
+ status = "disabled";
+ };
+
r_pio: pinctrl@01f02c00 {
compatible = "allwinner,sun8i-h3-r-pinctrl";
reg = <0x01f02c00 0x400>;
@@ -529,6 +547,13 @@
#gpio-cells = <3>;
interrupt-controller;
#interrupt-cells = <3>;
+
+ ir_pins_a: ir@0 {
+ allwinner,pins = "PL11";
+ allwinner,function = "s_cir_rx";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
};
};
};