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| author | Chen-Yu Tsai <wens@csie.org> | 2016-01-21 06:26:38 +0100 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2016-01-25 00:01:21 +0100 |
| commit | 74124439b93065c35b840f381bb26f61452c18e5 (patch) | |
| tree | dc33b4ce4eb5b7c9de4938de56558d6d84327a1b /arch/arm/boot/dts/sun9i-a80.dtsi | |
| parent | ARM: sun5i: chip: Add CPU regulator for cpufreq (diff) | |
| download | linux-74124439b93065c35b840f381bb26f61452c18e5.tar.xz linux-74124439b93065c35b840f381bb26f61452c18e5.zip | |
ARM: dts: sun8i: sina33: Enable hardware reset and HS-DDR for eMMC
mmc2 has a special pin for eMMC hardware reset, which is controllable
from the controller. Add the "mmc-cap-hw-reset" property to denote that
this controller supports this function, and the pins are actually used.
Also increase the signal drive strength for mmc2 pins, for HS-DDR mode
support.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun9i-a80.dtsi')
0 files changed, 0 insertions, 0 deletions