diff options
| author | Ondrej Jirman <megous@megous.com> | 2018-02-06 05:48:59 +0100 |
|---|---|---|
| committer | Chen-Yu Tsai <wens@csie.org> | 2018-04-20 08:39:12 +0200 |
| commit | 7824fcb38c1c9c9157ded239cdb78afe20115224 (patch) | |
| tree | b54b6734c5cbb761e482679feca6ff5f686b0153 /arch/arm/boot/dts/sunxi-h3-h5.dtsi | |
| parent | ARM: dts: sunxi: h3/h5: Add r_i2c pinmux node (diff) | |
| download | linux-7824fcb38c1c9c9157ded239cdb78afe20115224.tar.xz linux-7824fcb38c1c9c9157ded239cdb78afe20115224.zip | |
ARM: dts: sunxi: h3/h5: Add r_i2c I2C controller
Allwinner H3/H5 SoCs have an I2C controller at PL GPIO bank.
Add support for it in the device tree.
Signed-off-by: Ondrej Jirman <megous@megous.com>
[Icenowy: Change to use r_ccu and change pinmux node name]
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'arch/arm/boot/dts/sunxi-h3-h5.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/sunxi-h3-h5.dtsi | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 92b8fa96e737..c3bff1105e5d 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -822,6 +822,19 @@ status = "disabled"; }; + r_i2c: i2c@1f02400 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01f02400 0x400>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&r_i2c_pins>; + clocks = <&r_ccu CLK_APB0_I2C>; + resets = <&r_ccu RST_APB0_I2C>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun8i-h3-r-pinctrl"; reg = <0x01f02c00 0x400>; |