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authorLaxman Dewangan <ldewangan@nvidia.com>2013-01-29 13:56:18 +0100
committerStephen Warren <swarren@nvidia.com>2013-01-29 19:02:14 +0100
commitb16f9183c7c1918a3a5c36d35482f5e01dc9c384 (patch)
tree848ba71983a85bb287a7ee1d4f0b85318b9c324e /arch/arm/boot/dts/tegra114.dtsi
parentARM: tegra114: select PINCTRL for Tegra114 SoC (diff)
downloadlinux-b16f9183c7c1918a3a5c36d35482f5e01dc9c384.tar.xz
linux-b16f9183c7c1918a3a5c36d35482f5e01dc9c384.zip
ARM: DT: tegra114: add GPIO DT entry
Tegra114 has the GPIO controllers with 8 GPIO bank and each bank supports 32 pins. Add DT entry for GPIO controller. Tegra114 GPIO controller is compatible with Tegra30 GPIO controller driver. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra114.dtsi')
-rw-r--r--arch/arm/boot/dts/tegra114.dtsi17
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 366c177cba76..8f7ea189f6df 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -37,6 +37,23 @@
reg = <0x6000c004 0x14c>;
};
+ gpio: gpio {
+ compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
+ reg = <0x6000d000 0x1000>;
+ interrupts = <0 32 0x04
+ 0 33 0x04
+ 0 34 0x04
+ 0 35 0x04
+ 0 55 0x04
+ 0 87 0x04
+ 0 89 0x04
+ 0 125 0x04>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ };
+
serial@70006000 {
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
reg = <0x70006000 0x40>;