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| author | Thierry Reding <treding@nvidia.com> | 2021-12-07 10:56:21 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2021-12-14 16:07:42 +0100 |
| commit | 82d03bec4e97f01d982b1663d438c55b100de7e3 (patch) | |
| tree | 02e7edabe80c4001d0016a49ae33d4d93475693f /arch/arm/boot/dts/tegra114.dtsi | |
| parent | ARM: tegra: Fix compatible string for Tegra114+ timer (diff) | |
| download | linux-82d03bec4e97f01d982b1663d438c55b100de7e3.tar.xz linux-82d03bec4e97f01d982b1663d438c55b100de7e3.zip | |
ARM: tegra: Add #reset-cells for Tegra114 MC
The Tegra memory controller provides reset controls for hotflush reset,
so the #reset-cells property must be specified.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra114.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/tegra114.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 328425dba023..ce7410ee08b8 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -542,6 +542,7 @@ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + #reset-cells = <1>; #iommu-cells = <1>; }; |