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| author | Tuomas Tynkkynen <ttynkkynen@nvidia.com> | 2015-05-13 16:58:49 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2015-08-21 18:44:25 +0200 |
| commit | 0de088cc3463d451ca96439c723cc58932430820 (patch) | |
| tree | c7044eeb72a8339bbeb0a301eff7fdff9c3d6535 /arch/arm/boot/dts/tegra124.dtsi | |
| parent | ARM: tegra: Enable the DFLL on the Jetson TK1 (diff) | |
| download | linux-0de088cc3463d451ca96439c723cc58932430820.tar.xz linux-0de088cc3463d451ca96439c723cc58932430820.zip | |
ARM: tegra: Add entries for cpufreq on Tegra124
The Tegra124 cpufreq driver relies on certain clocks being present
in the /cpus/cpu@0 node.
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra124.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/tegra124.dtsi | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 5b8177a2456b..87318a72f615 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -947,6 +947,15 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; + + clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, + <&tegra_car TEGRA124_CLK_CCLK_LP>, + <&tegra_car TEGRA124_CLK_PLL_X>, + <&tegra_car TEGRA124_CLK_PLL_P>, + <&dfll>; + clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; + /* FIXME: what's the actual transition time? */ + clock-latency = <300000>; }; cpu@1 { |