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authorVenu Byravarasu <vbyravarasu@nvidia.com>2013-05-16 16:12:56 +0200
committerStephen Warren <swarren@nvidia.com>2013-05-18 00:22:05 +0200
commit9dffe3be3f321581c4510f2fa2e217b18c703bcd (patch)
tree671d71489dad5f1d1868f68a6eee654be4fa16d9 /arch/arm/boot/dts/tegra20-harmony.dts
parentARM: tegra: finalize USB EHCI and PHY bindings (diff)
downloadlinux-9dffe3be3f321581c4510f2fa2e217b18c703bcd.tar.xz
linux-9dffe3be3f321581c4510f2fa2e217b18c703bcd.zip
ARM: tegra: modify ULPI reset GPIO properties
1. All Tegra20 ULPI reset GPIO DT properties are modified to indicate active low nature of the GPIO. 2. Placed USB PHY DT node immediately below the EHCI controller DT nodes and corrected reg value in the name of USB PHY DT node. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra20-harmony.dts')
-rw-r--r--arch/arm/boot/dts/tegra20-harmony.dts10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index e7d5de4e00b9..e84f3f6a5392 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -430,15 +430,15 @@
usb@c5004000 {
status = "okay";
- nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+ nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
};
- usb@c5008000 {
- status = "okay";
+ usb-phy@c5004000 {
+ nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
};
- usb-phy@c5004400 {
- nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+ usb@c5008000 {
+ status = "okay";
};
sdhci@c8000200 {