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authorLucas Stach <l.stach@pengutronix.de>2014-03-05 14:25:46 +0100
committerStephen Warren <swarren@nvidia.com>2014-03-06 18:37:24 +0100
commit97070bd44bab603fc47063952250f479e9e7321e (patch)
treec65df2193bc7a0fbde2f134314f04c4c458b2536 /arch/arm/boot/dts/tegra20.dtsi
parentARM: tegra: use 2 address cells for Tegra124 DT (diff)
downloadlinux-97070bd44bab603fc47063952250f479e9e7321e.tar.xz
linux-97070bd44bab603fc47063952250f479e9e7321e.zip
ARM: dts: tegra: add PCIe interrupt mapping properties
Those are defined by the common PCI binding. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra20.dtsi')
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 480ecda3416b..52ef2cf0b142 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -552,6 +552,10 @@
GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
interrupt-names = "intr", "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+
bus-range = <0x00 0xff>;
#address-cells = <3>;
#size-cells = <2>;