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| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2018-08-16 10:06:04 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2018-09-26 16:42:57 +0200 |
| commit | 2db12b16e58a562fdf161b226739d30ea06bcd37 (patch) | |
| tree | c623b96fa5b04d554953f2d1b276067fb59f98e5 /arch/arm/boot/dts/tegra20.dtsi | |
| parent | ARM: dts: tegra20: restore address order (diff) | |
| download | linux-2db12b16e58a562fdf161b226739d30ea06bcd37.tar.xz linux-2db12b16e58a562fdf161b226739d30ea06bcd37.zip | |
ARM: dts: tegra20/tegra30: add pmu interrupt-affinity
This is similar to tegra124 and avoids the following being reported
upon boot:
hw perfevents: no interrupt-affinity property for /pmu, guessing.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra20.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/tegra20.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 80854f7de765..20869757d32f 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -865,5 +865,7 @@ compatible = "arm,cortex-a9-pmu"; interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&{/cpus/cpu@0}>, + <&{/cpus/cpu@1}>; }; }; |