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authorStephen Warren <swarren@nvidia.com>2013-01-23 17:43:49 +0100
committerStephen Warren <swarren@nvidia.com>2013-01-28 19:24:09 +0100
commitabf80c276dca1bf40b342b4ebf7815be0f6ba564 (patch)
tree4b90282b64e4f0b74200c120c96206c052dd6dfa /arch/arm/boot/dts/tegra30-beaver.dts
parentARM: tegra: Add Toradex Iris carrier board DT with T20 512MB COM (diff)
downloadlinux-abf80c276dca1bf40b342b4ebf7815be0f6ba564.tar.xz
linux-abf80c276dca1bf40b342b4ebf7815be0f6ba564.zip
ARM: tegra: move serial clock-frequency attr into the Tegra30 dtsi
No Tegra30 Platform is running PLL_P at another rate than 408MHz, nor is any using any other PLL as UART source clock. Move attribute into SoC level dtsi file to slim down board DT files. Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra30-beaver.dts')
-rw-r--r--arch/arm/boot/dts/tegra30-beaver.dts1
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 0f296a439eac..8ff2ff20e4a3 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -90,7 +90,6 @@
serial@70006000 {
status = "okay";
- clock-frequency = <408000000>;
};
i2c@7000c000 {