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author | Tony Lindgren <tony@atomide.com> | 2018-09-27 22:39:07 +0200 |
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committer | Tony Lindgren <tony@atomide.com> | 2018-10-18 19:04:02 +0200 |
commit | 4ed0dfe3cf39a97cd0ed532212b5e55e9752fe3f (patch) | |
tree | 57f0997e1826bab5fff31e2c633cfdaf4e967809 /arch/arm/boot/dts/tegra30-colibri-eval-v3.dts | |
parent | ARM: dts: dra7: Add l4 interconnect hierarchy and ti-sysc data (diff) | |
download | linux-4ed0dfe3cf39a97cd0ed532212b5e55e9752fe3f.tar.xz linux-4ed0dfe3cf39a97cd0ed532212b5e55e9752fe3f.zip |
ARM: dts: dra7: Move l4 child devices to probe them with ti-sysc
With l4 interconnect hierarchy and ti-sysc interconnect target module
data in place, we can simply move all the related child devices to
their proper location and enable probing using ti-sysc.
In general the first child device address range starts at range 0
from the ti-sysc interconnect target so the move involves adjusting
the child device reg properties for that.
In case of any regressions, problem devices can be reverted to probe
with legacy platform data as needed by moving them back and removing
the related interconnect target module node.
Cc: Dave Gerlach <d-gerlach@ti.com>
Cc: Keerthy <j-keerthy@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra30-colibri-eval-v3.dts')
0 files changed, 0 insertions, 0 deletions