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authorJay Agarwal <jagarwal@nvidia.com>2013-08-09 16:49:31 +0200
committerStephen Warren <swarren@nvidia.com>2013-08-12 22:20:43 +0200
commitd7283c11f7e87e40c44bbffc4397309ef8bc5c7b (patch)
tree74a3df2d33b2dc77af29b3385c62497dce14b9eb /arch/arm/boot/dts/tegra30.dtsi
parentARM: tegra: Fix Beaver's PCIe lane configuration (diff)
downloadlinux-d7283c11f7e87e40c44bbffc4397309ef8bc5c7b.tar.xz
linux-d7283c11f7e87e40c44bbffc4397309ef8bc5c7b.zip
ARM: dts: tegra: Increase prefetchable PCI memory space
Instead of evenly splitting the 512 MiB area between prefetchable and non-prefetchable memory spaces, increase the prefetchable memory space to 384 MiB while at the same time decreasing the non-prefetchable memory space to 128 MiB. This is a more useful default as most PCIe devices require more prefetchable than non-prefetchable memory. Signed-off-by: Jay Agarwal <jagarwal@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra30.dtsi')
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index c8faccad0e65..d81c52e5b358 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -35,8 +35,8 @@
0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
- 0x82000000 0 0x20000000 0x20000000 0 0x10000000 /* non-prefetchable memory */
- 0xc2000000 0 0x30000000 0x30000000 0 0x10000000>; /* prefetchable memory */
+ 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
+ 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
clocks = <&tegra_car TEGRA30_CLK_PCIE>,
<&tegra_car TEGRA30_CLK_AFI>,