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| author | Thierry Reding <treding@nvidia.com> | 2015-01-08 13:24:33 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2015-01-09 11:45:15 +0100 |
| commit | 2cda1880f8c6b6a081ab78824d3742a229887b69 (patch) | |
| tree | 91c638cbd3bf58518453fbcfb8fc3d281892a3f6 /arch/arm/boot/dts/tegra30.dtsi | |
| parent | ARM: dts: tegra20: fix GR3D, DSI unit and reg base addresses (diff) | |
| download | linux-2cda1880f8c6b6a081ab78824d3742a229887b69.tar.xz linux-2cda1880f8c6b6a081ab78824d3742a229887b69.zip | |
ARM: tegra: Fix unit address for Cortex-A9 TWD timer
The Cortex-A9 TWD timer has registers at address 0x50040600, but the
unit address was 50004600, most likely a typo.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra30.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/tegra30.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 99475f6e76a3..db4810df142c 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -225,7 +225,7 @@ }; }; - timer@50004600 { + timer@50040600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x50040600 0x20>; interrupts = <GIC_PPI 13 |