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authorDietmar Eggemann <dietmar.eggemann@arm.com>2017-08-30 16:41:19 +0200
committerKrzysztof Kozlowski <krzk@kernel.org>2017-09-17 09:35:55 +0200
commit178465474c216439e3b683017a11a5c68ea0c05a (patch)
tree0ee735bcae03e63c082dea5ce394291ec40c84a0 /arch/arm/boot/dts/uniphier-sld8.dtsi
parentARM: dts: exynos: add exynos5420 cpu capacity-dmips-mhz information (diff)
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ARM: dts: exynos: add exynos5422 cpu capacity-dmips-mhz information
The following 'capacity-dmips-mhz' dt property values are used: Cortex-A15: 1024, Cortex-A7: 539 They have been derived form the cpu_efficiency values: Cortex-A15: 3891, Cortex-A7: 2048 by scaling them so that the Cortex-A15s (big cores) use 1024. The cpu_efficiency values were originally derived from the "Big.LITTLE Processing with ARM Cortex™-A15 & Cortex-A7" white paper (http://www.cl.cam.ac.uk/~rdm34/big.LITTLE.pdf). Table 1 lists 1.9x (3891/2048) as the Cortex-A15 vs Cortex-A7 performance ratio for the Dhrystone benchmark. The following platforms are affected once cpu-invariant accounting support is re-connected to the task scheduler: odroidxu3, odroidxu3-lite, odroidxu4 Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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