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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2019-06-21 12:53:16 +0200 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2019-06-25 17:06:50 +0200 |
| commit | bc8841f0c1e6945fd7fde6faad3300d1b08abd86 (patch) | |
| tree | eb3a16a4d6deb350109c1155a29f34c441212d5f /arch/arm/boot/dts/uniphier-sld8.dtsi | |
| parent | Linux 5.2-rc1 (diff) | |
| download | linux-bc8841f0c1e6945fd7fde6faad3300d1b08abd86.tar.xz linux-bc8841f0c1e6945fd7fde6faad3300d1b08abd86.zip | |
ARM: dts: uniphier: update to new Denali NAND binding
With commit d8e8fd0ebf8b ("mtd: rawnand: denali: decouple controller
and NAND chips"), the Denali NAND controller driver migrated to the
new controller/chip representation.
Update DT for it.
In the new binding, the number of connected chips are described in
DT instead of run-time probed.
I added just one chip to the reference boards, where we do not know
if the on-board NAND device is a single chip or multiple chips.
If we added too many chips into DT, it would end up with the timeout
error in nand_scan_ident().
I changed all the pinctrl properties to use the single CS.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/boot/dts/uniphier-sld8.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/uniphier-sld8.dtsi | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi index efce02768b6f..cbebb6e4c616 100644 --- a/arch/arm/boot/dts/uniphier-sld8.dtsi +++ b/arch/arm/boot/dts/uniphier-sld8.dtsi @@ -407,9 +407,11 @@ status = "disabled"; reg-names = "nand_data", "denali_reg"; reg = <0x68000000 0x20>, <0x68100000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 65 4>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand2cs>; + pinctrl-0 = <&pinctrl_nand>; clock-names = "nand", "nand_x", "ecc"; clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; |