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authorStefan Agner <stefan@agner.ch>2016-10-18 03:51:27 +0200
committerShawn Guo <shawnguo@kernel.org>2016-10-24 14:05:32 +0200
commit44d524218c65e1f2e6d945b09165562852298015 (patch)
tree85d12c637cc229a76cfb68ffb4e459c654106cc2 /arch/arm/boot/dts/vf500.dtsi
parentARM: imx: gpc: Fix the imx_gpc_genpd_init() error path (diff)
downloadlinux-44d524218c65e1f2e6d945b09165562852298015.tar.xz
linux-44d524218c65e1f2e6d945b09165562852298015.zip
ARM: dts: vf610: fix IRQ flag of global timer
The global timer IRQ (PPI[0], PPI 11 in device tree terms) is a rising edge interrupt. The ARM Cortex-A5 MPCore TRM in Chapter 10.1.2. Interrupt types and sources says: "Interrupt is rising-edge sensitive." The bits seem to be read-only, hence this missconfiguration had no negative effect. However, with commit 992345a58e0c ("irqchip/gic: WARN if setting the interrupt type for a PPI fails") warnings such as this get printed: GIC: PPI11 is secure or misconfigured With this change the new configuration matches the default configuration and no warning is printed anymore. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/vf500.dtsi')
-rw-r--r--arch/arm/boot/dts/vf500.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi
index a3824e61bd72..d7fdb2a7d97b 100644
--- a/arch/arm/boot/dts/vf500.dtsi
+++ b/arch/arm/boot/dts/vf500.dtsi
@@ -70,7 +70,7 @@
global_timer: timer@40002200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x40002200 0x20>;
- interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
interrupt-parent = <&intc>;
clocks = <&clks VF610_CLK_PLATFORM_BUS>;
};