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authorPeter Crosthwaite <crosthwaitepeter@gmail.com>2014-12-01 01:25:50 +0100
committerMichal Simek <michal.simek@xilinx.com>2014-12-01 09:22:53 +0100
commit7b01abb06c997e5431cdfc62267449aaef1d77c7 (patch)
tree198f04d9bd4ca8c4ea15d41a09da04c40aad3a27 /arch/arm/boot/dts/zynq-zybo.dts
parentarm: dts: zynq: Move crystal freq. to board level (diff)
downloadlinux-7b01abb06c997e5431cdfc62267449aaef1d77c7.tar.xz
linux-7b01abb06c997e5431cdfc62267449aaef1d77c7.zip
arm: dts: zynq: Add Digilent ZYBO board
Add a DTS describing the Digilent ZYBO board. Similar to ZED but with a 50MHz crystal instead of 33MHz. Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/boot/dts/zynq-zybo.dts')
-rw-r--r--arch/arm/boot/dts/zynq-zybo.dts52
1 files changed, 52 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/zynq-zybo.dts b/arch/arm/boot/dts/zynq-zybo.dts
new file mode 100644
index 000000000000..a9a12ce5023b
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-zybo.dts
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2011 - 2014 Xilinx
+ * Copyright (C) 2012 National Instruments Corp.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+
+/ {
+ model = "Zynq ZYBO Development Board";
+ compatible = "digilent,zynq-zybo", "xlnx,zynq-7000";
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x20000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyPS0,115200 earlyprintk";
+ };
+
+};
+
+&clkc {
+ ps-clk-frequency = <50000000>;
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <&ethernet_phy>;
+
+ ethernet_phy: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&sdhci0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};