diff options
| author | Troy Kisky <troy.kisky@boundarydevices.com> | 2013-12-13 02:49:07 +0100 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2014-02-09 14:29:19 +0100 |
| commit | f17e2a31c2f1a1d64e5a9a1f4fc26c44a4c11f0e (patch) | |
| tree | 2723070b5d46ce7b06a16b57e018eed761a6ce0f /arch/arm/boot/dts | |
| parent | ARM: dts: imx6qdl-sabrelite: Add uart1 support (diff) | |
| download | linux-f17e2a31c2f1a1d64e5a9a1f4fc26c44a4c11f0e.tar.xz linux-f17e2a31c2f1a1d64e5a9a1f4fc26c44a4c11f0e.zip | |
ARM: dts: imx6qdl-sabrelite: remove usdhc4 wp-gpio
On Sabre Lite usdhc4 is a micro sd slot, which has no
write protect.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts')
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi index 2a0c5fbbf6cb..82b728375070 100644 --- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi @@ -115,7 +115,6 @@ pinctrl_hog: hoggrp { fsl,pins = < MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 - MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 @@ -285,7 +284,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc4>; cd-gpios = <&gpio2 6 0>; - wp-gpios = <&gpio2 7 0>; vmmc-supply = <®_3p3v>; status = "okay"; }; |