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| author | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2014-04-25 10:45:18 +0200 |
|---|---|---|
| committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2015-06-04 08:01:23 +0200 |
| commit | b21a9c3ee83ab26fd33c9a5f3bc2150c95eea975 (patch) | |
| tree | 866677c74841d0f5fecfdb45162f480a9b39a270 /arch/arm/boot/dts | |
| parent | CLK: TI: always enable DESHDCP clock (diff) | |
| download | linux-b21a9c3ee83ab26fd33c9a5f3bc2150c95eea975.tar.xz linux-b21a9c3ee83ab26fd33c9a5f3bc2150c95eea975.zip | |
arm/dts: dra7xx: add 'ti,set-rate-parent' for dss_dss_clk
We need set-rate-parent flags for the display's clock path so that the
DSS driver can change the clock rate of the PLL.
This patchs adds the ti,set-rate-parent flag to 'dss_dss_clk' clock
node, which is only a gate clock, allowing the setting of the clock rate
to propagate to the PLL.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: devicetree@vger.kernel.org
Acked-by: Tero Kristo <t-kristo@ti.com>
Diffstat (limited to 'arch/arm/boot/dts')
| -rw-r--r-- | arch/arm/boot/dts/dra7xx-clocks.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 470f39c4e326..357bedeebfac 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1531,6 +1531,7 @@ clocks = <&dpll_per_h12x2_ck>; ti,bit-shift = <8>; reg = <0x1120>; + ti,set-rate-parent; }; dss_hdmi_clk: dss_hdmi_clk { |