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| author | Boris Brezillon <boris.brezillon@free-electrons.com> | 2015-08-18 10:08:56 +0200 |
|---|---|---|
| committer | Gregory CLEMENT <gregory.clement@free-electrons.com> | 2015-09-29 16:19:11 +0200 |
| commit | 35e5bb58dbf6c7b309387a83ffa04584d669ef8b (patch) | |
| tree | c70dc7b6330f478c0a894133be2ada4561d5a799 /arch/arm/boot/dts | |
| parent | ARM: mvebu: define crypto SRAM ranges for all armada-370 boards (diff) | |
| download | linux-35e5bb58dbf6c7b309387a83ffa04584d669ef8b.tar.xz linux-35e5bb58dbf6c7b309387a83ffa04584d669ef8b.zip | |
ARM: mvebu: add crypto related nodes to armada 375 dtsi
Add crypto related nodes in armada-375.dtsi.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts')
| -rw-r--r-- | arch/arm/boot/dts/armada-375.dtsi | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index e9a381741ce1..7ccce7529b0c 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -513,6 +513,21 @@ }; }; + crypto@90000 { + compatible = "marvell,armada-375-crypto"; + reg = <0x90000 0x10000>; + reg-names = "regs"; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gateclk 30>, <&gateclk 31>, + <&gateclk 28>, <&gateclk 29>; + clock-names = "cesa0", "cesa1", + "cesaz0", "cesaz1"; + marvell,crypto-srams = <&crypto_sram0>, + <&crypto_sram1>; + marvell,crypto-sram-size = <0x800>; + }; + sata@a0000 { compatible = "marvell,orion-sata"; reg = <0xa0000 0x5000>; @@ -619,5 +634,23 @@ }; }; + + crypto_sram0: sa-sram0 { + compatible = "mmio-sram"; + reg = <MBUS_ID(0x09, 0x09) 0 0x800>; + clocks = <&gateclk 30>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>; + }; + + crypto_sram1: sa-sram1 { + compatible = "mmio-sram"; + reg = <MBUS_ID(0x09, 0x05) 0 0x800>; + clocks = <&gateclk 31>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>; + }; }; }; |