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| author | Luca Weiss <luca@z3ntu.xyz> | 2022-10-02 14:28:58 +0200 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2022-11-06 04:02:41 +0100 |
| commit | 4dd3949d17b66144fe7c39cf68ff4bedb4154f61 (patch) | |
| tree | 557b143de54354d8925145965d1395fcbfdd42ab /arch/arm/boot/dts | |
| parent | ARM: dts: qcom: msm8226: Add CCI bus (diff) | |
| download | linux-4dd3949d17b66144fe7c39cf68ff4bedb4154f61.tar.xz linux-4dd3949d17b66144fe7c39cf68ff4bedb4154f61.zip | |
ARM: dts: qcom: msm8974: Add CCI bus
Add a node for the Camera Control Interface I2C bus found on MSM8974.
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Signed-off-by: Matti Lehtimäki <matti.lehtimaki@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221002122859.75525-7-matti.lehtimaki@gmail.com
Diffstat (limited to 'arch/arm/boot/dts')
| -rw-r--r-- | arch/arm/boot/dts/qcom-msm8974.dtsi | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 7647cf9f2f76..56bbe8784c22 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1464,6 +1464,38 @@ bias-pull-up; }; + cci_default: cci-default-state { + cci_i2c0_default: cci-i2c0-default-pins { + pins = "gpio19", "gpio20"; + function = "cci_i2c0"; + drive-strength = <2>; + bias-disable; + }; + + cci_i2c1_default: cci-i2c1-default-pins { + pins = "gpio21", "gpio22"; + function = "cci_i2c1"; + drive-strength = <2>; + bias-disable; + }; + }; + + cci_sleep: cci-sleep-state { + cci_i2c0_sleep: cci-i2c0-sleep-pins { + pins = "gpio19", "gpio20"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + cci_i2c1_sleep: cci-i2c1-sleep-pins { + pins = "gpio21", "gpio22"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + spi8_default: spi8_default { mosi { pins = "gpio45"; @@ -1616,6 +1648,40 @@ }; }; + cci: cci@fda0c000 { + compatible = "qcom,msm8974-cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfda0c000 0x1000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; + clocks = <&mmcc CAMSS_TOP_AHB_CLK>, + <&mmcc CAMSS_CCI_CCI_AHB_CLK>, + <&mmcc CAMSS_CCI_CCI_CLK>; + clock-names = "camss_top_ahb", + "cci_ahb", + "cci"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cci_default>; + pinctrl-1 = <&cci_sleep>; + + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + gpu: adreno@fdb00000 { compatible = "qcom,adreno-330.1", "qcom,adreno"; reg = <0xfdb00000 0x10000>; |