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authorGary Bisson <bisson.gary@gmail.com>2014-12-04 00:03:51 +0100
committerShawn Guo <shawn.guo@linaro.org>2014-12-29 12:23:34 +0100
commit81ef447950bf0955aca46f4a7617d8ce435cf0ce (patch)
treee7240d24e566664e5120a8adc582d73f96d8c5fb /arch/arm/boot
parentARM: dts: imx6qdl: Fix CODA960 interrupt order (diff)
downloadlinux-81ef447950bf0955aca46f4a7617d8ce435cf0ce.tar.xz
linux-81ef447950bf0955aca46f4a7617d8ce435cf0ce.zip
ARM: clk-imx6q: fix video divider for rev T0 1.0
The post dividers do not work on i.MX6Q rev T0 1.0 so they must be fixed to 1. As the table index was wrong, a divider a of 4 could still be requested which implied the clock not to be set properly. This is the root cause of the HDMI not working at high resolution on rev T0 1.0 of the SoC. Signed-off-by: Gary Bisson <bisson.gary@gmail.com> Cc: <stable@vger.kernel.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot')
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