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authorRob Herring <rob.herring@calxeda.com>2013-07-23 21:04:44 +0200
committerRobert Richter <rric@kernel.org>2013-11-05 00:01:05 +0100
commit982ac2a7b757708845df4339243a91ba180a5744 (patch)
treee366d9410351cdafbbe712aac71c552a1a3e35c9 /arch/arm/boot
parentedac, highbank: Fix interrupt setup of mem and l2 controller (diff)
downloadlinux-982ac2a7b757708845df4339243a91ba180a5744.tar.xz
linux-982ac2a7b757708845df4339243a91ba180a5744.zip
ARM: dts: calxeda: move memory-controller node out of ecx-common.dtsi
The DDR controller is slightly different in ECX-2000 and ECX-1000, so we need to have different nodes for each platform. Signed-off-by: Rob Herring <rob.herring@calxeda.com> [Device Tree documentation updated.] Signed-off-by: Robert Richter <rric@kernel.org>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/ecx-2000.dts6
-rw-r--r--arch/arm/boot/dts/ecx-common.dtsi6
-rw-r--r--arch/arm/boot/dts/highbank.dts6
3 files changed, 12 insertions, 6 deletions
diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts
index 139b40cc3a23..2ccbb57fbfa8 100644
--- a/arch/arm/boot/dts/ecx-2000.dts
+++ b/arch/arm/boot/dts/ecx-2000.dts
@@ -85,6 +85,12 @@
<1 10 0xf08>;
};
+ memory-controller@fff00000 {
+ compatible = "calxeda,ecx-2000-ddr-ctrl";
+ reg = <0xfff00000 0x1000>;
+ interrupts = <0 91 4>;
+ };
+
intc: interrupt-controller@fff11000 {
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;
diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi
index e8559b753c9d..f95988ff61d4 100644
--- a/arch/arm/boot/dts/ecx-common.dtsi
+++ b/arch/arm/boot/dts/ecx-common.dtsi
@@ -45,12 +45,6 @@
status = "disabled";
};
- memory-controller@fff00000 {
- compatible = "calxeda,hb-ddr-ctrl";
- reg = <0xfff00000 0x1000>;
- interrupts = <0 91 4>;
- };
-
ipc@fff20000 {
compatible = "arm,pl320", "arm,primecell";
reg = <0xfff20000 0x1000>;
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
index 6aad34ad9517..ed14aeac0566 100644
--- a/arch/arm/boot/dts/highbank.dts
+++ b/arch/arm/boot/dts/highbank.dts
@@ -86,6 +86,12 @@
soc {
ranges = <0x00000000 0x00000000 0xffffffff>;
+ memory-controller@fff00000 {
+ compatible = "calxeda,hb-ddr-ctrl";
+ reg = <0xfff00000 0x1000>;
+ interrupts = <0 91 4>;
+ };
+
timer@fff10600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xfff10600 0x20>;