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| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2017-10-31 23:23:16 +0100 |
|---|---|---|
| committer | Kevin Hilman <khilman@baylibre.com> | 2017-12-07 02:03:46 +0100 |
| commit | 6844e968b54977a1ad55cf8e80c6598369cacff8 (patch) | |
| tree | 9cbd9b743855648e8431363edfdd17fb1794f95f /arch/arm/boot | |
| parent | ARM: dts: meson8b: add more L2 cache settings (diff) | |
| download | linux-6844e968b54977a1ad55cf8e80c6598369cacff8.tar.xz linux-6844e968b54977a1ad55cf8e80c6598369cacff8.zip | |
ARM: dts: meson8: add more L2 cache settings
Amlogic's vendor kernel prints these PL310 L2 cache controller settings
during boot:
8 ways, 4096 sets, CACHE_ID 0x4100a0c9, Cache size: 1048576 B
AUX_CTRL 0x7ec80001, PERFETCH_CTRL 0x71000007, POWER_CTRL 0x00000000
TAG_LATENCY 0x00000111, DATA_LATENCY 0x00000222
Add the "prefetch-data", "prefetch-instr" and "arm,shared-override"
properties to get the same L2 cache controller configuration as the
vendor kernel.
Two differences still remain:
- L310_AUX_CTRL_NS_INT_CTRL is currently not supported by the cache-l2x0
driver
- bit 23 is set by the vendor kernel, but this is defined in cache-l2x0.h
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/meson8.dtsi | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 2d7a0752a460..af3aa7058c5a 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -308,6 +308,9 @@ arm,data-latency = <3 3 3>; arm,tag-latency = <2 2 2>; arm,filter-ranges = <0x100000 0xc0000000>; + prefetch-data = <1>; + prefetch-instr = <1>; + arm,shared-override; }; &pwm_ab { |