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authorGeert Uytterhoeven <geert+renesas@glider.be>2016-01-29 11:17:18 +0100
committerSimon Horman <horms+renesas@verge.net.au>2016-02-09 19:43:24 +0100
commit8a758a9493d8cac4afde82918590a11bbb24c85c (patch)
tree87e627e58656d35a450db61598d8cfe1e6000539 /arch/arm/boot
parentARM: dts: r8a7794: Add BRG support for (H)SCIF (diff)
downloadlinux-8a758a9493d8cac4afde82918590a11bbb24c85c.tar.xz
linux-8a758a9493d8cac4afde82918590a11bbb24c85c.zip
ARM: dts: alt: Enable SCIF_CLK frequency and pins
Add and enable the external crystal for the SCIF_CLK and its pinctrl, to be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF. This increases the range and accuracy of supported baud rates. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/r8a7794-alt.dts13
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 773f304d1142..ca9bc4fff287 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -103,6 +103,9 @@
};
&pfc {
+ pinctrl-0 = <&scif_clk_pins>;
+ pinctrl-names = "default";
+
du_pins: du {
renesas,groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0";
renesas,function = "du";
@@ -113,6 +116,11 @@
renesas,function = "scif2";
};
+ scif_clk_pins: scif_clk {
+ renesas,groups = "scif_clk";
+ renesas,function = "scif_clk";
+ };
+
ether_pins: ether {
renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
renesas,function = "eth";
@@ -205,6 +213,11 @@
status = "okay";
};
+&scif_clk {
+ clock-frequency = <14745600>;
+ status = "okay";
+};
+
&qspi {
pinctrl-0 = <&qspi_pins>;
pinctrl-names = "default";