diff options
| author | Thomas Gleixner <tglx@linutronix.de> | 2006-07-01 23:32:14 +0200 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-07-01 23:32:14 +0200 |
| commit | c4bfa28aec58c588de55babe99f4c172ec534704 (patch) | |
| tree | dc105fc1c44b26e19a82b076b37370812192bd0c /arch/arm/common/gic.c | |
| parent | [ARM] 3692/1: ARM: coswitch irq handling to the generic implementation (diff) | |
| download | linux-c4bfa28aec58c588de55babe99f4c172ec534704.tar.xz linux-c4bfa28aec58c588de55babe99f4c172ec534704.zip | |
[ARM] 3686/1: ARM: arm/common: convert irq handling
Patch from Thomas Gleixner
From: Thomas Gleixner <tglx@linutronix.de>
Convert the files in arch/arm/common to use the generic
irq handling functions.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/common/gic.c')
| -rw-r--r-- | arch/arm/common/gic.c | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index c02dc8116a18..f3c1ebfdd0aa 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -33,6 +33,7 @@ static void __iomem *gic_dist_base; static void __iomem *gic_cpu_base; +static DEFINE_SPINLOCK(irq_controller_lock); /* * Routines to acknowledge, disable and enable interrupts @@ -52,32 +53,45 @@ static void __iomem *gic_cpu_base; static void gic_ack_irq(unsigned int irq) { u32 mask = 1 << (irq % 32); + + spin_lock(&irq_controller_lock); writel(mask, gic_dist_base + GIC_DIST_ENABLE_CLEAR + (irq / 32) * 4); writel(irq, gic_cpu_base + GIC_CPU_EOI); + spin_unlock(&irq_controller_lock); } static void gic_mask_irq(unsigned int irq) { u32 mask = 1 << (irq % 32); + + spin_lock(&irq_controller_lock); writel(mask, gic_dist_base + GIC_DIST_ENABLE_CLEAR + (irq / 32) * 4); + spin_unlock(&irq_controller_lock); } static void gic_unmask_irq(unsigned int irq) { u32 mask = 1 << (irq % 32); + + spin_lock(&irq_controller_lock); writel(mask, gic_dist_base + GIC_DIST_ENABLE_SET + (irq / 32) * 4); + spin_unlock(&irq_controller_lock); } #ifdef CONFIG_SMP -static void gic_set_cpu(struct irqdesc *desc, unsigned int irq, unsigned int cpu) +static void gic_set_cpu(unsigned int irq, cpumask_t mask_val) { void __iomem *reg = gic_dist_base + GIC_DIST_TARGET + (irq & ~3); unsigned int shift = (irq % 4) * 8; + unsigned int cpu = first_cpu(mask_val); u32 val; + spin_lock(&irq_controller_lock); + irq_desc[irq].cpu = cpu; val = readl(reg) & ~(0xff << shift); val |= 1 << (cpu + shift); writel(val, reg); + spin_unlock(&irq_controller_lock); } #endif @@ -86,7 +100,7 @@ static struct irqchip gic_chip = { .mask = gic_mask_irq, .unmask = gic_unmask_irq, #ifdef CONFIG_SMP - .set_cpu = gic_set_cpu, + .set_affinity = gic_set_cpu, #endif }; |