diff options
| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-01-06 23:31:35 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-01-06 23:32:03 +0100 |
| commit | 4ec3eb13634529c0bc7466658d84d0bbe3244aea (patch) | |
| tree | b491daac2ccfc7b8ca88e171a43f66888463568a /arch/arm/common | |
| parent | ARM: DMA: add support for DMA debugging (diff) | |
| parent | ARM: TWD: enable one-shot mode (diff) | |
| download | linux-4ec3eb13634529c0bc7466658d84d0bbe3244aea.tar.xz linux-4ec3eb13634529c0bc7466658d84d0bbe3244aea.zip | |
Merge branch 'smp' into misc
Conflicts:
arch/arm/kernel/entry-armv.S
arch/arm/mm/ioremap.c
Diffstat (limited to 'arch/arm/common')
| -rw-r--r-- | arch/arm/common/gic.c | 28 |
1 files changed, 24 insertions, 4 deletions
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index ada6359160eb..772f95f1aecd 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -251,15 +251,16 @@ void __init gic_dist_init(unsigned int gic_nr, void __iomem *base, writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); /* - * Set priority on all interrupts. + * Set priority on all global interrupts. */ - for (i = 0; i < max_irq; i += 4) + for (i = 32; i < max_irq; i += 4) writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4); /* - * Disable all interrupts. + * Disable all interrupts. Leave the PPI and SGIs alone + * as these enables are banked registers. */ - for (i = 0; i < max_irq; i += 32) + for (i = 32; i < max_irq; i += 32) writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32); /* @@ -277,11 +278,30 @@ void __init gic_dist_init(unsigned int gic_nr, void __iomem *base, void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base) { + void __iomem *dist_base; + int i; + if (gic_nr >= MAX_GIC_NR) BUG(); + dist_base = gic_data[gic_nr].dist_base; + BUG_ON(!dist_base); + gic_data[gic_nr].cpu_base = base; + /* + * Deal with the banked PPI and SGI interrupts - disable all + * PPI interrupts, ensure all SGI interrupts are enabled. + */ + writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR); + writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET); + + /* + * Set priority on PPI and SGI interrupts + */ + for (i = 0; i < 32; i += 4) + writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4); + writel(0xf0, base + GIC_CPU_PRIMASK); writel(1, base + GIC_CPU_CTRL); } |